Electrostatic discharge protection device

ABSTRACT

An electrostatic discharge (ESD) protection device for providing an ESD path between two circuitries is provided. Each circuitry has a power supply terminal and a ground terminal. The protection device comprises an equivalent MOS, a first terminal, and a second terminal. The equivalent MOS comprises a source, a drain and a gate, wherein the drain is connected to the gate. The first terminal is connected to the gate, while the second terminal is connected to the source. The first terminal is connected to one power supply terminal and ground terminal, whereas the second terminal is connected to the other the power supply terminal and ground terminal.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a Divisional of co-pending application Ser. No.11/724,194, filed on Mar. 15, 2007, the entire contents of which arehereby incorporated by reference and for which priority is claimed under35 U.S.C. § 120. This nonprovisional application also claims priorityunder 35 U.S.C. § 119(a) on Taiwan Patent Application No. 095135789filed on Sep. 27, 2006, the entirety of which is herein incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electrostatic discharge protectiondevice. More particularly, the present invention relates to anelectrostatic discharge protection device for providing an electrostaticdischarge path between two circuitries.

2. Descriptions of the Related Art

An electrostatic discharge phenomenon releases energy to a circuitry,causing a temporarily high voltage and current in the circuitry. Thishigh voltage and current may damage the circuitry in a chip. Forexample, it may damage internal circuits, or the internal conductingwire. Thus, it is important to provide a non-damaging electrostaticdischarge path between internal circuits.

Conventional solutions have placed power cut cells between two internalcircuits. The power cut cell is generally a power cut diode combinationcomprising two power cut diode modules configured to conduct in contrarydirections. The combination can be set between two power supplyterminals or two ground terminals, as shown in FIG. 1.

FIG. 1 shows two power cut diode combinations 11, 12. The power cutdiode combination 11 connects power supply terminals VCC1 and VCC2,while the power cut diode combination 12 connects ground terminals GND1and GND2. The power cut diode combination 11 comprises two power cutdiode modules 111 and 112 configured to conduct in contrary directions.In addition, the power cut diode combination 12 comprises two power cutdiode modules 121 and 122 configured to conduct in contrary directions.The power supply terminals and ground terminals respectively connectwith the electrostatic discharge (ESD) protection device (not shown inFIG. 1) for conducting ESD energy out of the circuitry. Meanwhile, theturn-on voltage of the diode can block noise flowing between the twointernal circuits when the power cut diode is not turned on.

The operations of the power cut diode combinations 11, 12 are describedas follows. When an ESD phenomenon occurs on the VCC1, a temporary highvoltage occurs. At this time, an ESD protection device connected to theVCC1 forces the ESD energy out of the circuitry. In addition, the powercut diode module 111 guides the ESD energy to the VCC2, so an ESDprotection device connected to the VCC2 can force the ESD energy out ofthe circuitry jointly. By the same principle, when the ESD phenomenonoccurs on the VCC2, the power cut diode module 112 can guide the ESDenergy to the VCC1. The power cut diode combination 12 operates in asimilar way and forces the ESD energy out of the circuitry.

The equivalent model of a diode can be simply realized as combination ofan ideal diode and an internal resistor in series, as shown in FIG. 2.FIG. 2 shows an ideal diode 21 and an internal resistor 22 in series,where the ideal diode 22 has an input 211 and an output 212. The idealdiode 21 is presumed to have a threshold voltage without an internalresistor. When the differential voltage caused by the input 211 and theoutput 212 is higher than the threshold voltage, the ideal diode 21turns on, and the current flows through the internal resistor 22 and outthe output 212. Thus, when the electrostatic discharge energy turns onthe ideal diode 21, a voltage is produced by the two ends of theinternal resistor 22 due to the flowing current. As a result, theelectrostatic discharge energy is more or less blocked by the internalresistor 22. However, there are drawbacks of applying a combination ofpower cut diodes as a power cut cell.

The aforementioned drawbacks would diminish electrostatic dischargeprotection. However, conventional technology is not capable of providinga power cut cell that has a low internal resistor when it turns on, andblocks the noise when it turns off.

Therefore, an electrostatic discharge protection device with a lowinternal resistor and a noise blocking ability is needed in thesemiconductor industry.

SUMMARY OF THE INVENTION

The primary objective of this invention is to provide an electrostaticdischarge protection device to provide an electrostatic discharge pathbetween two circuits, with each of the circuits having a power supplyterminal and a ground terminal. The electrostatic discharge protectiondevice comprises an equivalent MOS with a source, a drain and a gate,the drain connecting to the gate, a first end connecting to the gate,and a second end connecting to the source. The first end connects to thepower supply terminal and ground terminal of one circuit. The second endconnects to the power supply terminal and ground terminal of the othercircuit, respectively.

Another objective of this invention is to provide an electrostaticdischarge protection device array to provide an electrostatic dischargepath between two circuits. The electrostatic discharge protection devicearray comprises a first end, a second end, and a plurality of equivalentMOSs in series, with each equivalent MOS having a source, a drain, and agate. The plurality of equivalent MOSs has a first equivalent MOS and alast equivalent MOS. The first end connects to a gate of the firstequivalent MOS, and the second end connects to a source of the lastequivalent MOS. Each MOS has its drain connecting to its gate, whileeach source of the MOS connects to the gate of the next MOS. The firstend connects to a power supply terminal and a ground terminal of onecircuit. The second end connects to a power supply terminal and a groundterminal of another circuit, respectively.

Thus, the invention provides an ESD protection device with a lowinternal resistor, and the turn-on voltage of the ESD protection deviceblocks noise from getting into the circuitry.

The detailed technology and preferred embodiments implemented for thesubject invention are described in the following paragraphs accompanyingthe appended drawings for people skilled in this field to wellappreciate the features of the claimed invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conventional electrostatic discharge protection structure;

FIG. 2 is an equivalent model of a diode;

FIG. 3 is a first embodiment of the present invention;

FIG. 4( a) is a second embodiment of the present invention;

FIG. 4( b) is a third embodiment of the present invention; and

FIG. 5 is a fourth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3 is a first embodiment of the present invention. An ESD protectiondevice 3 is equivalent to an N-type MOS (NMOS) device, and comprises adrain 31 with N+ dopant, a source 32 with N+ dopant, a gate 33, a heavydoping region 34 with P+ dopant, a P-type substrate 35, a first end 301,and a second end 302. The symbol “+” means “heavy doping” herein. Thedrain 31, gate 33, and first end 301 are electrically connected. Thesource 32 and the heavy doping region 34 are electrically connected toform a body contact. The source 32 is also connected to the second end302.

The first end 301 is adapted to connect to the ground GND1 of aninternal circuit. Meanwhile the second end 302 is adapted to connect tothe ground GND2 of another internal circuit. When a high voltage causedby ESD is present at the GND1, the high voltage is applied to the gate33. The voltage difference of the gate 33 and the source 32 is thenlarge enough to turn on the ESD protection device 3. When the ESDprotection device 3 turns on, it acquires a low turn-on resistor; theESD energy can thus, be transmitted from the GND1 to the GND2 via theESD protection device 3.

A second embodiment of the present invention comprises a protectiondevice 3 and a protection device 4 conducted in the opposite directionto prevent the ESD from communicating with the GND1 or GND2. Theprotection device 3 and the protection device 4 are in-parallel andconnected to the GND1 and the GND2. FIG. 4( a) shows the secondembodiment, wherein the protection device 3 comprises a first end 301connecting to the GND1 and a second end 302 connecting to the GND2. Aplurality of protection devices can be arranged in parallel to provide alarger threshold voltage and thus gain better noise-blockingcapabilities. FIG. 4( b) shows a third embodiment of the presentinvention, wherein a protection device 41 is in-parallel with aprotection device 42 to provide ESD protection, and another protectiondevice 43 is in-parallel with its respective protection device 44.

FIG. 5 shows a fourth embodiment of the present invention. An ESDprotection device 5 is equivalent to a P-type MOS (PMOS) device. ThePMOS comprises a drain 51 with P+ dopant, a source 52 with P+ dopant, agate 53, a heavy doping region with N+ dopant, a Nwell 55, a P substrate56, a first end 501 and a second end 502. The Nwell 55 is adapted to abody of the PMOS. The drain 51, gate 53, and first end 501 areelectrically connected together. The source 52 and the heavy dopingregion 54 are electrically connected to form a body contact. Inaddition, the source 32 connects to the second end 502. The Nwell 55 isequivalent to a substantial substrate, which means that when a PMOS isbased on a P substrate, it needs to form an N well first to isolate thelater formed drain and source from the P substrate.

Since the protection device 5 is within a P substrate, and the Psubstrate connects to the lowest voltage level of a chip, the first end501 and the second end 502 are able to connect to power supply terminalsVCC1 and VCC2, or to ground terminals GND1 and GND2.

Similarly, once the protection device is within an N substrate andformed with an NMOS, the protection device is able to connect to thepower supply terminals or ground terminals. As a result, the device canbe applied to a different substrate without substantially changing theprotection. People skilled in the art can understand and practice theprotection device within an N substrate by reviewing the aforementioneddisclosure, thus, the same descriptions are omitted.

To outline the specifics of the present invention, this followingexample will address the connection of two power supply terminals VCC1and VCC2 using the protection device 5, with the first end 501 connectedto the VCC1, and the second end 502 connected to the VCC2. When there isa high voltage due to the presence of an ESD at the VCD2, the highvoltage also carries through to the source 52. The voltage difference ofthe gate 53 and the source 52 is then large enough to turn on the ESDprotection device 5. When the ESD protection device 5 turns on, itacquires a low turn-on resistor so that the ESD energy can betransmitted from the VCC2 to the VCC1 via the ESD protection device 5.

Similarly, the protection device 5 can join another protection devicethat is conducted in an opposite direction to prevent the ESD from beingpresent at the VCC1 or VCC2. Also, a plurality of protection devicesin-series can provide a better noise-blocking effect. People skilled inthe art can understand and practice various combinations of protectiondevices by reviewing the aforementioned disclosure. Thus, the redundantdescriptions are omitted.

The present invention is thus advantageous in providing an ESDprotection device with a low internal resistor.

The above disclosure is related to the detailed technical contents andinventive features thereof. People skilled in this field may proceedwith a variety of modifications and replacements based on thedisclosures and suggestions of the invention as described withoutdeparting from the characteristics thereof. Nevertheless, although suchmodifications and replacements are not fully disclosed in the abovedescriptions, they have substantially been covered in the followingclaims as appended.

1. An electrostatic discharge protection device which is adapted toprovide an electrostatic discharge path between two circuits, eachhaving a power supply terminal and a ground terminal, the protectiondevice comprising: an equivalent MOS having a source, a drain and a gatewhich connects to the drain; a first end connecting to the gate, and asecond end connecting to the source; wherein the first end connects toone of the power supply terminal and the ground terminal of one of thecircuits, and the second end connects to one of the power supplyterminal and the ground terminal of the other circuit, the equivalentMOS is a PMOS within an N substrate, the first end connects to the powersupply terminal of one of the circuits, and the second end connects tothe power supply terminal of the other circuit.
 2. An electrostaticdischarge protection device array which is adapted to provide anelectrostatic discharge path between two circuits, comprising: aplurality of equivalent MOSs in series, each having a source, a drain,and a gate, and the plurality of equivalent MOSs having a firstequivalent MOS and a last equivalent MOS; a first end connecting to agate of the first equivalent MOS; and a second end connecting to asource of the last equivalent MOS; wherein the drain of each of the MOSsconnects to its gate, its source connects to a gate of a next MOS; thefirst end connects to one of a power supply terminal and a groundterminal of one of the circuits, and the second end connects to one of apower supply terminal and a ground terminal of the other circuit, eachof the equivalent MOSs is a PMOS within an N substrate, the first endconnects to the power supply terminal of one of the circuits, and thesecond end connects to the power supply terminal of the other circuit.